1. Field of the Invention
The present invention relates generally to a memory system, and more specifically, to a memory system having efficient write-to-read turnaround utilizing read posting.
2. Discussion of the Related Art
In a conventional memory device, such as a dynamic random access memory (DRAM), after a write (Wr) command is issued to the memory device, a certain amount of time lapses before the write data is transported onto the main bus (i.e., the central processing unit (CPU) bus) and written to the memory device. The column-strobe-address (CAS) read latency time, also known as xe2x80x9ctCLxe2x80x9d, is the time period that lapses between the issuance of a read or write command and the output of data onto the main bus. After the write data is outputted onto the main bus, a certain amount of time is required for the write data to be transported from the main bus, to the input/output interface of the memory device, and written to the memory device. This time period is the write CAS recovery period, also known as xe2x80x9ctWRxe2x80x9d. Generally, an action such as a read (Rd) command may not be performed by the memory device during the tWR period.
Because the tWR period may each be several clock periods long (each clock period being the time of a clock cycle), periods of inactivity during the tWR period do not allow the memory device to operate most efficiently. When taken in the aggregate, the tWR periods that occur for each write operation may add up to a significant amount of time where no read (Rd) command operations may be performed. When the memory device is unable to perform operations at certain times, the main bus becomes unsaturated, meaning that the main bus is not utilized most efficiently by not carrying as much data as it is able to handle. A memory device could operate more efficiently and quickly if the memory device could perform operations that can provide more data onto the main bus sooner.